Two CAN buses, one 64 MHz counter. Every frame below was received by the VHDL design in simulation, packed into its UART format and decoded here, in your browser, from the raw bytes. Each frame on CAN0 was forwarded to CAN1 by a simulated gateway. The brackets are that gateway's latency, measured by the hardware to one clock (15.625 ns).
Loading the tb_gateway capture…
CAN0 frame
CAN1 frame
data phase (BRS, 2 Mbit/s)
gateway latency
Scroll to zoom, drag to pan, click a frame to inspect it. Frame boxes are drawn from the decoded length and bit rates (stuff bits not counted); the left edge of each box is the hardware timestamp.
Packet
Click a frame on the timeline.